Sukanta Dey, Ph.D. Senior EDA Engineer Custom Design Solution (CDS) Group Physical Design, Physical Verification, and Parasitic Extraction Intel Corporation Santa Clara, CA 95054, US M.Tech.-Ph.D. (IIT Guwahati, 2021) Postdoc Research (ECE, U Florida, Sept 2021 to Feb 2023) Homepage: https://thesukantadey.github.io/

About

Sukanta is working as a Senior EDA Engineer at Intel Corporation, Santa Clara, CA. Previously, he was a Postdoctoral Research Associate at the Department of Electrical and Computer Engineering (ECE), University of Florida, Gainesville, FL, US. He received his Master’s and Ph.D. from the Department of Computer Science and Engineering, IIT Guwahati in March 2021, specializing in Machine Learning techniques for Electronic Design Automation (EDA). His Ph.D. thesis title is "Design Methodology for On-Chip Power Grid Interconnect: AI/ML Perspective". Prior to joining IIT Guwahati, he received his Bachelor's in Electronics and Telecommunication Engineering from Assam Engineering College in July 2014. His domain of expertise includes EDA, VLSI CAD, VLSI Physical Design, Machine Learning for VLSI CAD, Custom IC Design (Analog and Mixed Signal), RTL to GDS2 Flow (ASIC Design), and Hardware Security/Security-Aware EDA.

Professional Experience

• Senior EDA Engineer, Intel Corporation, Santa Clara, California, US (April 2023 to Present)

• Lead EDA Postdoctoral Researcher, Dept. of ECE, University of Florida, Gainesville, Florida, US (September 2021 to February 2023)

• EDA Research Scholar, Dept. of CSE, IIT Guwahati, Assam, INDIA (July 2014 to July 2021)

• Project Intern, Texas Instruments, Bengaluru, Karnataka, INDIA (December 2015)

Educations

• MTech + PhD, Computer Scinece and Engineering, IIT Guwahati (July 2014 to March 2021)

• B.E., Electronics and Telecommunication Engineering, Assam Engineering College (August 2010 to July 2014)

Research interests

• VLSI CAD/Electronic Design Automation (EDA) and Desgin for Manufacturability(DFM)/ Reliability(DFR) for System-on-Chip (SoC).

• More-than-Moore interconnects for Multicore processor/ Multiprocessor SoC (MPSoC) - 3D IC, Network-on-Chip, Optical, Wireless.

• Machine Learning, Combinatorial Optimization, and Computational Intelligence.

• Hardware and Systems Security, Adversarial Machine Learning, Cryptography, Internet-of-Things (IoT).

TPC Member/Paper Reviewer/Expert Reviewer

• Intel Design and Test Technology Conference (DTTC) (Intel Internal Conference)

• IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)

• ACM Transactions on Design Automation of Electronic Systems (TODAES)

• IEEE Transactions on VLSI Systems (TVLSI)

• ACM Transactions on Embedded Computing Systems (TECS)

• ACM/IEEE Design Automation Conference (DAC)

• IEEE Symposium on Security and Privacy (S&P) [Shadow PC]

• IEEE International Symposium on Hardware Oriented Security and Trust (HOST) [TPC Member]

• International Conference on VLSI Design (VLSID) [TPC Member]

• IEEE Access

• Journal of Electronic Materials, Springer

• IET Computer and Digital Techniques

• IET Circuits, Devices, and Systems

• Journal of Circuits, Systems, and Computers

• IET Signal Processing

• IET Image Processing

• IET Electronics Letters

• IET Wireless Sensor Systems

• International Conference on Soft Computing for Problem Solving (SocPros)

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