The objective of this area is to develop CAD tools for solving various issues that arise in the SoC/chip design cycle. My primary focus is on developing various CAD tools for the VLSI physical design flow. I have worked on several projects related to the development of CAD tools for physical design. This includes a stochastic DC and transient analysis tool, an IR drop estimation tool, an electromigration-aware aging estimation tool, and a secure physical design and verification tool.

The objective of this area is to develop CAD tools for the design, analysis, and optimization of More-than-Moore interconnects, encompassing 3D IC, NoC, Chiplets, and photonic IC. So far, I have worked on TSV-based 3D IC tool development. In the future, I plan to explore other areas.

The objective of this part is to design a framework for predictive modeling and estimation using Machine Learning in VLSI CAD. Most VLSI CAD problems can be transformed into combinatorial optimization problems. Therefore, another objective in this part is to formulate VLSI CAD problems as combinatorial optimization problems and solve them with the help of Computational Intelligence or Nature-Inspired Algorithms. For machine learning approaches, we consider data-driven methods. I have also worked on a few ML-related VLSI CAD problems.

In this part, the objective is to design a secure system. Vulnerabilities may arise from various levels of abstraction. However, we should design the system to mitigate vulnerabilities as much as possible. In that direction, we are addressing security and privacy issues related to hardware design flow from the circuit level to the system level to the application level. We are also considering security issues in machine learning systems and security design challenges in Internet-of-Things (IoT) systems.